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| author | whitequark <whitequark@whitequark.org> | 2020-06-11 22:21:30 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-12 00:31:57 +0000 |
| commit | cd7bf115b668da8e59b07b939ab17771da983983 (patch) | |
| tree | a795988016443dfab582a3b4afbc3593a457c136 /examples/intel | |
| parent | 8a4841d78690313a91af97e8c6d9aa3e65a3e491 (diff) | |
| download | yosys-cd7bf115b668da8e59b07b939ab17771da983983.tar.gz yosys-cd7bf115b668da8e59b07b939ab17771da983983.tar.bz2 yosys-cd7bf115b668da8e59b07b939ab17771da983983.zip | |
cxxrtl: simplify unbuffering of input wires.
This also fixes an edge case with (*keep*) input ports.
Diffstat (limited to 'examples/intel')
0 files changed, 0 insertions, 0 deletions