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| author | Xark <Xark@XarkLabs.com> | 2020-06-14 00:45:22 -0700 |
|---|---|---|
| committer | Xark <Xark@XarkLabs.com> | 2020-06-14 00:45:22 -0700 |
| commit | 9509444ef2a55dcd75a6f5e1d96337f442238cee (patch) | |
| tree | 02d6ba48fbcb13b469f23818767d7389ae3e9205 /examples/intel/MAX10/runme_postsynth | |
| parent | 74e93e083ff23f3381fe2409e5847f9843840b17 (diff) | |
| download | yosys-9509444ef2a55dcd75a6f5e1d96337f442238cee.tar.gz yosys-9509444ef2a55dcd75a6f5e1d96337f442238cee.tar.bz2 yosys-9509444ef2a55dcd75a6f5e1d96337f442238cee.zip | |
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
Diffstat (limited to 'examples/intel/MAX10/runme_postsynth')
0 files changed, 0 insertions, 0 deletions