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| author | Jannis Harder <me@jix.one> | 2022-05-20 21:46:39 +0200 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-05-30 09:11:31 -0400 |
| commit | 4bfaaea0d52c235bb51c4dc54b07fe301eebe473 (patch) | |
| tree | ff66a42daace95c965c6851036f907771d61af25 /examples/intel/MAX10/runme_postsynth | |
| parent | ce24208a8bf74c25868c5073b0ff68a76b71d99f (diff) | |
| download | yosys-4bfaaea0d52c235bb51c4dc54b07fe301eebe473.tar.gz yosys-4bfaaea0d52c235bb51c4dc54b07fe301eebe473.tar.bz2 yosys-4bfaaea0d52c235bb51c4dc54b07fe301eebe473.zip | |
verilog: fix size and signedness of array querying functions
genrtlil.cc and simplify.cc had inconsistent and slightly broken
handling of signedness for array querying functions. These functions are
defined to return a signed result. Simplify always produced an unsigned
and genrtlil always a signed 32-bit result ignoring the context.
Includes tests for the the relvant edge cases for context dependent
conversions.
Diffstat (limited to 'examples/intel/MAX10/runme_postsynth')
0 files changed, 0 insertions, 0 deletions