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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-05 09:08:04 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-05 09:08:04 -0800 |
| commit | 1a260ce89b79f0d4c2092f725b48583bd5e7bc41 (patch) | |
| tree | bef82baea6124458d7acc43bddbcfa990ee81876 /examples/intel/MAX10/runme_postsynth | |
| parent | 2d98db73e39f17865ae26cdd00cf7c112521649f (diff) | |
| parent | 43030db5fff285de85096aaf5578b0548659f6b7 (diff) | |
| download | yosys-1a260ce89b79f0d4c2092f725b48583bd5e7bc41.tar.gz yosys-1a260ce89b79f0d4c2092f725b48583bd5e7bc41.tar.bz2 yosys-1a260ce89b79f0d4c2092f725b48583bd5e7bc41.zip | |
Merge pull request #712 from mmicko/anlogic-support
Initial support for Anlogic FPGA
Diffstat (limited to 'examples/intel/MAX10/runme_postsynth')
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