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author | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
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committer | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
commit | b34385ec924b6067c1f82bdbae923f8062518956 (patch) | |
tree | 3d09d194e53fa575628b890df7cc106efdcd4742 /examples/cmos/counter_tb.v | |
parent | b0ac32bc03b340b26e0d3bb778af1c915722abdf (diff) | |
download | yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.gz yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.bz2 yosys-b34385ec924b6067c1f82bdbae923f8062518956.zip |
Completed ngspice digital example with verilog tb
Diffstat (limited to 'examples/cmos/counter_tb.v')
-rw-r--r-- | examples/cmos/counter_tb.v | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/examples/cmos/counter_tb.v b/examples/cmos/counter_tb.v new file mode 100644 index 000000000..bcd7d992c --- /dev/null +++ b/examples/cmos/counter_tb.v @@ -0,0 +1,33 @@ +module counter_tb; + + /* Make a reset pulse and specify dump file */ + reg reset = 0; + initial begin + $dumpfile("counter_tb.vcd"); + $dumpvars(0,counter_tb); + + # 0 reset = 1; + # 4 reset = 0; + # 36 reset = 1; + # 4 reset = 0; + # 6 $finish; + end + + /* Make enable with period of 8 and 6,7 low */ + reg en = 1; + always begin + en = 1; + #6; + en = 0; + #2; + end + + /* Make a regular pulsing clock. */ + reg clk = 0; + always #1 clk = !clk; + + /* UUT */ + wire [2:0] count; + counter c1 (clk, reset, en, count); + +endmodule |