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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-07 22:44:50 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-07 22:44:50 -0800 |
| commit | e9b34ad5c07935454367af1bee1248371d214fc9 (patch) | |
| tree | 09a476af058604639d6a0cf96d4720ff7300ab25 /examples/anlogic | |
| parent | a330c6836318d43d52cda68959f2b86c2b2ede9c (diff) | |
| parent | df0598f455990604f51cb309831e1b95193d2dc3 (diff) | |
| download | yosys-e9b34ad5c07935454367af1bee1248371d214fc9.tar.gz yosys-e9b34ad5c07935454367af1bee1248371d214fc9.tar.bz2 yosys-e9b34ad5c07935454367af1bee1248371d214fc9.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'examples/anlogic')
| -rw-r--r-- | examples/anlogic/.gitignore | 5 | ||||
| -rw-r--r-- | examples/anlogic/README | 1 | ||||
| -rw-r--r-- | examples/anlogic/build.tcl | 2 | ||||
| -rw-r--r-- | examples/anlogic/demo.adc | 2 | ||||
| -rw-r--r-- | examples/anlogic/demo.v | 10 | ||||
| -rw-r--r-- | examples/anlogic/demo.ys | 2 |
6 files changed, 12 insertions, 10 deletions
diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore index fa9424cd8..97c978a15 100644 --- a/examples/anlogic/.gitignore +++ b/examples/anlogic/.gitignore @@ -1,4 +1,7 @@ demo.bit demo_phy.area full.v -*.log
\ No newline at end of file +*.log +*.h +*.tde +*.svf diff --git a/examples/anlogic/README b/examples/anlogic/README index 99143cce0..35d8e9cb1 100644 --- a/examples/anlogic/README +++ b/examples/anlogic/README @@ -10,4 +10,3 @@ set TD_HOME env variable to the full path to the TD <TD Install Directory> as fo export TD_HOME=<TD Install Directory> then run "bash build.sh" in this directory. - diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl index db8c3b347..06db525c9 100644 --- a/examples/anlogic/build.tcl +++ b/examples/anlogic/build.tcl @@ -8,4 +8,4 @@ pack place route report_area -io_info -file demo_phy.area -bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000 +bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000 diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc index c8fbaed3e..ec802502e 100644 --- a/examples/anlogic/demo.adc +++ b/examples/anlogic/demo.adc @@ -1,2 +1,2 @@ set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ -set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED
\ No newline at end of file +set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v index a7edf4e37..e17db771e 100644 --- a/examples/anlogic/demo.v +++ b/examples/anlogic/demo.v @@ -1,18 +1,18 @@ module demo ( - input wire CLK_IN, - output wire R_LED + input wire CLK_IN, + output wire R_LED ); parameter time1 = 30'd12_000_000; reg led_state; reg [29:0] count; - + always @(posedge CLK_IN)begin if(count == time1)begin - count<= 30'd0; + count<= 30'd0; led_state <= ~led_state; end else count <= count + 1'b1; end assign R_LED = led_state; -endmodule
\ No newline at end of file +endmodule diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys index 5687bcd31..cb396cc2b 100644 --- a/examples/anlogic/demo.ys +++ b/examples/anlogic/demo.ys @@ -1,3 +1,3 @@ read_verilog demo.v synth_anlogic -top demo -write_verilog full.v
\ No newline at end of file +write_verilog full.v |