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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:59:19 -0700 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:59:19 -0700 |
commit | f1a8e8a480a7a88835b02abafd27c03e90de7041 (patch) | |
tree | 49679db03662de0b029d814354f01f972179e453 /examples/anlogic/demo.v | |
parent | 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75 (diff) | |
parent | f0b2d8e467998876ad2cc14232d30ff7892982a3 (diff) | |
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Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'examples/anlogic/demo.v')
-rw-r--r-- | examples/anlogic/demo.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v new file mode 100644 index 000000000..e17db771e --- /dev/null +++ b/examples/anlogic/demo.v @@ -0,0 +1,18 @@ +module demo ( + input wire CLK_IN, + output wire R_LED +); + parameter time1 = 30'd12_000_000; + reg led_state; + reg [29:0] count; + + always @(posedge CLK_IN)begin + if(count == time1)begin + count<= 30'd0; + led_state <= ~led_state; + end + else + count <= count + 1'b1; + end + assign R_LED = led_state; +endmodule |