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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 08:56:37 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 08:56:37 -0700 |
| commit | 991c2ca95bfac2bedd9fd622dbef15611021a8be (patch) | |
| tree | d97236975007054d0c294c79420207efacf94a72 /examples/aiger | |
| parent | ebb059896a55efacf1d90f78dbd25faff30969e2 (diff) | |
| download | yosys-991c2ca95bfac2bedd9fd622dbef15611021a8be.tar.gz yosys-991c2ca95bfac2bedd9fd622dbef15611021a8be.tar.bz2 yosys-991c2ca95bfac2bedd9fd622dbef15611021a8be.zip | |
Add comment on why we have to match for clock-enable/reset muxes
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