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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 17:13:27 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 17:13:27 -0800 |
| commit | f24de88f385a3eeaadd9b9c8c200a7c338f37448 (patch) | |
| tree | 27fefa8cdfebbfaa98d4443501def3fd3ce61298 /backends | |
| parent | 28f814ee59e36230200108381a9c674c5275e3e4 (diff) | |
| download | yosys-f24de88f385a3eeaadd9b9c8c200a7c338f37448.tar.gz yosys-f24de88f385a3eeaadd9b9c8c200a7c338f37448.tar.bz2 yosys-f24de88f385a3eeaadd9b9c8c200a7c338f37448.zip | |
log_debug() for abc9_{arrival,required} times
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cde53ff63..359d951b9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -254,6 +254,14 @@ struct XAigerWriter log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); auto jt = arrivals.begin(); + +#ifndef NDEBUG + if (ys_debug(1)) { + static std::set<std::pair<IdString,IdString>> seen; + if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); + } +#endif + for (auto bit : sigmap(conn.second)) { arrival_times[bit] = *jt; if (arrivals.size() > 1) |