diff options
author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-01 16:21:13 -0700 |
---|---|---|
committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-01 16:21:13 -0700 |
commit | 6ea09caf01cf06ad7f93eb62fa85ec9361b7e5a1 (patch) | |
tree | ca3bc94a15cc9eb641d1a4de0645c24fe0f06010 /backends | |
parent | 7a0af004a0a4dc3831997f0845d40fc3ea514281 (diff) | |
download | yosys-6ea09caf01cf06ad7f93eb62fa85ec9361b7e5a1.tar.gz yosys-6ea09caf01cf06ad7f93eb62fa85ec9361b7e5a1.tar.bz2 yosys-6ea09caf01cf06ad7f93eb62fa85ec9361b7e5a1.zip |
Re-indent firrtl.cc:struct memory - no functional change.
Diffstat (limited to 'backends')
-rw-r--r-- | backends/firrtl/firrtl.cc | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index a8a1bb078..9feff71c6 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -163,20 +163,20 @@ struct FirrtlWorker } }; /* Memories defined within this module. */ - struct memory { - Cell *pCell; // for error reporting - string name; // memory name - int abits; // number of address bits - int size; // size (in units) of the memory - int width; // size (in bits) of each element - int read_latency; - int write_latency; - vector<read_port> read_ports; - vector<write_port> write_ports; - std::string init_file; - std::string init_file_srcFileSpec; - string srcLine; - memory(Cell *pCell, string name, int abits, int size, int width) : pCell(pCell), name(name), abits(abits), size(size), width(width), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") { + struct memory { + Cell *pCell; // for error reporting + string name; // memory name + int abits; // number of address bits + int size; // size (in units) of the memory + int width; // size (in bits) of each element + int read_latency; + int write_latency; + vector<read_port> read_ports; + vector<write_port> write_ports; + std::string init_file; + std::string init_file_srcFileSpec; + string srcLine; + memory(Cell *pCell, string name, int abits, int size, int width) : pCell(pCell), name(name), abits(abits), size(size), width(width), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") { // Provide defaults for abits or size if one (but not the other) is specified. if (this->abits == 0 && this->size != 0) { this->abits = ceil_log2(this->size); @@ -206,18 +206,18 @@ struct FirrtlWorker } return srcLine.c_str(); } - void add_memory_read_port(read_port &rp) { - read_ports.push_back(rp); - } - void add_memory_write_port(write_port &wp) { - write_ports.push_back(wp); - } - void add_memory_file(std::string init_file, std::string init_file_srcFileSpec) { - this->init_file = init_file; - this->init_file_srcFileSpec = init_file_srcFileSpec; - } + void add_memory_read_port(read_port &rp) { + read_ports.push_back(rp); + } + void add_memory_write_port(write_port &wp) { + write_ports.push_back(wp); + } + void add_memory_file(std::string init_file, std::string init_file_srcFileSpec) { + this->init_file = init_file; + this->init_file_srcFileSpec = init_file_srcFileSpec; + } - }; + }; dict<string, memory> memories; void register_memory(memory &m) |