diff options
| author | David Shah <dave@ds0.me> | 2020-04-14 20:39:13 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-04-14 20:39:13 +0100 |
| commit | 3b85b7c57a071279275f27d5547a5ad4ad2e1a44 (patch) | |
| tree | 7c588bc2ac73131864f87d9240a6e063067ac461 /backends | |
| parent | 7a36728b2fd640e166188b05c901b1992ec2af6b (diff) | |
| download | yosys-3b85b7c57a071279275f27d5547a5ad4ad2e1a44.tar.gz yosys-3b85b7c57a071279275f27d5547a5ad4ad2e1a44.tar.bz2 yosys-3b85b7c57a071279275f27d5547a5ad4ad2e1a44.zip | |
cxxrtl: Fix handling of unclocked memory read ports
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/cxxrtl/cxxrtl.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc index 3263f03fd..d1a855bf0 100644 --- a/backends/cxxrtl/cxxrtl.cc +++ b/backends/cxxrtl/cxxrtl.cc @@ -871,7 +871,8 @@ struct CxxrtlWorker { dump_sigspec_rhs(cell->getPort(ID(ADDR))); f << ", " << memory->start_offset << ", " << memory->size << ");\n"; if (cell->type == ID($memrd)) { - if (!cell->getPort(ID(EN)).is_fully_ones()) { + bool has_enable = cell->getParam(ID(CLK_ENABLE)).as_bool() && !cell->getPort(ID(EN)).is_fully_ones(); + if (has_enable) { f << indent << "if ("; dump_sigspec_rhs(cell->getPort(ID(EN))); f << ") {\n"; @@ -930,7 +931,7 @@ struct CxxrtlWorker { f << " = value<" << memory->width << "> {};\n"; dec_indent(); f << indent << "}\n"; - if (!cell->getPort(ID(EN)).is_fully_ones()) { + if (has_enable) { dec_indent(); f << indent << "}\n"; } |