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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 20:26:09 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 20:26:09 -0700 |
commit | 375fcbe5113db80a92b950e5aca7df17add67acf (patch) | |
tree | 525511c0557870db4889566ea033d0dc066cc562 /backends | |
parent | 9f608d6be30c9302c0e3810525457e39f57b0334 (diff) | |
download | yosys-375fcbe5113db80a92b950e5aca7df17add67acf.tar.gz yosys-375fcbe5113db80a92b950e5aca7df17add67acf.tar.bz2 yosys-375fcbe5113db80a92b950e5aca7df17add67acf.zip |
abc_flop to also get topologically sorted
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 82c28549c..5eeae3b82 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -312,19 +312,18 @@ struct XAigerWriter undriven_bits.erase(O); ff_bits.emplace_back(q); } - else { - for (const auto &conn : cell->connections()) { - if (cell->input(conn.first)) { - // Ignore inout for the sake of topographical ordering - if (cell->output(conn.first)) continue; - for (auto bit : sigmap(conn.second)) - bit_users[bit].insert(cell->name); - } - if (cell->output(conn.first)) - for (auto bit : sigmap(conn.second)) - bit_drivers[bit].insert(cell->name); + for (const auto &conn : cell->connections()) { + if (cell->input(conn.first)) { + // Ignore inout for the sake of topographical ordering + if (cell->output(conn.first)) continue; + for (auto bit : sigmap(conn.second)) + bit_users[bit].insert(cell->name); } + + if (cell->output(conn.first)) + for (auto bit : sigmap(conn.second)) + bit_drivers[bit].insert(cell->name); } } else { |