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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
| commit | 12c10892e6783e0a1ef52776c232dd342745543f (patch) | |
| tree | 52482dfe8d609403b743698116e889599a5f19db /backends | |
| parent | c10e96c9ec8c4e56935ba796af0fa3d1f22b2a71 (diff) | |
| parent | 7c57d8fbb44cdc466f4e384528109ada7e52b4c1 (diff) | |
| download | yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.gz yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.bz2 yosys-12c10892e6783e0a1ef52776c232dd342745543f.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index fb0add847..bdf705056 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -678,6 +678,23 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) #undef HANDLE_UNIOP #undef HANDLE_BINOP + if (cell->type == "$shiftx") + { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = "); + dump_sigspec(f, cell->getPort("\\A")); + f << stringf("["); + if (cell->getParam("\\B_SIGNED").as_bool()) + f << stringf("$signed("); + dump_sigspec(f, cell->getPort("\\B")); + if (cell->getParam("\\B_SIGNED").as_bool()) + f << stringf(")"); + f << stringf(" +: %d", cell->getParam("\\Y_WIDTH").as_int()); + f << stringf("];\n"); + return true; + } + if (cell->type == "$mux") { f << stringf("%s" "assign ", indent.c_str()); |