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| author | whitequark <whitequark@whitequark.org> | 2018-12-13 04:36:02 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-16 15:22:34 +0000 |
| commit | fccaa25ec1b053259a377991d8deba0f71021956 (patch) | |
| tree | 0577b77893356c3eddde3e6ace210ccbdbd10d7b /backends/verilog | |
| parent | 435776120a40ed06ea42ca63bcca231913507ac3 (diff) | |
| download | yosys-fccaa25ec1b053259a377991d8deba0f71021956.tar.gz yosys-fccaa25ec1b053259a377991d8deba0f71021956.tar.bz2 yosys-fccaa25ec1b053259a377991d8deba0f71021956.zip | |
write_verilog: add a missing newline.
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index dde03f920..850abfad7 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1419,7 +1419,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n" "can't always be mapped directly to Verilog always blocks. Unintended\n" "changes in simulation behavior are possible! Use \"proc\" to convert\n" - "processes to logic networks and registers.", log_id(module)); + "processes to logic networks and registers.\n", log_id(module)); f << stringf("\n"); for (auto it = module->processes.begin(); it != module->processes.end(); ++it) |