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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-08 14:42:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-08 14:42:08 -0800 |
| commit | fb6df09dd210faddf1d238d2605e645bdbda9723 (patch) | |
| tree | 2530b2a4fdf426c67ae034fe23b6b45db9838ada /backends/verilog | |
| parent | 8886fa5506b227229398e5ac884203e799bce22c (diff) | |
| parent | e8f4dc739c5cf1129800aaa88df3f7c6f9c99360 (diff) | |
| download | yosys-fb6df09dd210faddf1d238d2605e645bdbda9723.tar.gz yosys-fb6df09dd210faddf1d238d2605e645bdbda9723.tar.bz2 yosys-fb6df09dd210faddf1d238d2605e645bdbda9723.zip | |
Merge remote-tracking branch 'origin/dff_init' into read_aiger
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 66a9e70d3..7b3a60e61 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); std::string init; - if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { std::stringstream ss; dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); init = ss.str(); |