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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-13 00:43:15 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-14 01:06:23 +0200 |
| commit | f7913285067ed30bf5087f265db7e0bd523af2b6 (patch) | |
| tree | 520728e6d67c91e4597d39d3f04cd8d75d931156 /backends/verilog | |
| parent | 1f74ec3535dba67d3e71ab1b9bf509c86bdca560 (diff) | |
| download | yosys-f7913285067ed30bf5087f265db7e0bd523af2b6.tar.gz yosys-f7913285067ed30bf5087f265db7e0bd523af2b6.tar.bz2 yosys-f7913285067ed30bf5087f265db7e0bd523af2b6.zip | |
Add opt_mem_widen pass.
If all of us are wide, then none of us are!
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions