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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-16 16:45:49 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-16 16:45:49 +0100 |
| commit | ddff75b60ab6b29bbc8425c7f5ac2e6ebbbf32a6 (patch) | |
| tree | f84ec451a7499847bcc3311f3eb504367681a6a5 /backends/verilog | |
| parent | 5fa5dbbddab03af89e00426e21df9f30d020a94e (diff) | |
| parent | f6412d71099ff31fe899e0e982df99c3c8bc98aa (diff) | |
| download | yosys-ddff75b60ab6b29bbc8425c7f5ac2e6ebbbf32a6.tar.gz yosys-ddff75b60ab6b29bbc8425c7f5ac2e6ebbbf32a6.tar.bz2 yosys-ddff75b60ab6b29bbc8425c7f5ac2e6ebbbf32a6.zip | |
Merge pull request #736 from whitequark/select_assert_list
select: print selection if a -assert-* flag causes an error
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 922b4c44c..3a47b478f 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1421,7 +1421,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n" "can't always be mapped directly to Verilog always blocks. Unintended\n" "changes in simulation behavior are possible! Use \"proc\" to convert\n" - "processes to logic networks and registers.", log_id(module)); + "processes to logic networks and registers.\n", log_id(module)); f << stringf("\n"); for (auto it = module->processes.begin(); it != module->processes.end(); ++it) |