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| author | N. Engelhardt <nak@yosyshq.com> | 2022-08-25 11:41:12 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-25 11:41:12 +0200 |
| commit | 8e640663d6b7ff84043068f48ed5f3cf7bff4321 (patch) | |
| tree | 59001b194c2f573674c37352733427a3ec28a1c1 /backends/verilog | |
| parent | 029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff) | |
| parent | 9465b2af95a146f514fc1e0b2d31bc3d9a233fb7 (diff) | |
| download | yosys-8e640663d6b7ff84043068f48ed5f3cf7bff4321.tar.gz yosys-8e640663d6b7ff84043068f48ed5f3cf7bff4321.tar.bz2 yosys-8e640663d6b7ff84043068f48ed5f3cf7bff4321.zip | |
Merge pull request #3457 from KrystalDelusion/docs_width
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index aa1d4558c..e60ebc70e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2160,7 +2160,8 @@ struct VerilogBackend : public Backend { log(" as binary numbers.\n"); log("\n"); log(" -simple-lhs\n"); - log(" Connection assignments with simple left hand side without concatenations.\n"); + log(" Connection assignments with simple left hand side without\n"); + log(" concatenations.\n"); log("\n"); log(" -extmem\n"); log(" instead of initializing memories using assignments to individual\n"); |