diff options
| author | whitequark <whitequark@whitequark.org> | 2018-12-07 18:48:06 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-07 18:55:08 +0000 |
| commit | 7fe770a441a129c509fd4da04b60ada942a28bc8 (patch) | |
| tree | 03cb149cb5da3a9638b5919019db38ee6b754db7 /backends/verilog | |
| parent | 435776120a40ed06ea42ca63bcca231913507ac3 (diff) | |
| download | yosys-7fe770a441a129c509fd4da04b60ada942a28bc8.tar.gz yosys-7fe770a441a129c509fd4da04b60ada942a28bc8.tar.bz2 yosys-7fe770a441a129c509fd4da04b60ada942a28bc8.zip | |
write_verilog: correctly map RTLIL `sync init`.
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index dde03f920..922b4c44c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo if (sync->type == RTLIL::STa) { f << stringf("%s" "always @* begin\n", indent.c_str()); + } else if (sync->type == RTLIL::STi) { + f << stringf("%s" "initial begin\n", indent.c_str()); } else { f << stringf("%s" "always @(", indent.c_str()); if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1) |