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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-22 04:05:30 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-22 04:05:30 +0100 |
| commit | 7b01ba384f1374d6a6fb3d40d7dc5fd03d50ac31 (patch) | |
| tree | d01e93a0ea13a31c4d2812e3db11bec2fac198cb /backends/verilog | |
| parent | 1c4a6411af4339a26d28d1e4b93cd2c44eb16228 (diff) | |
| download | yosys-7b01ba384f1374d6a6fb3d40d7dc5fd03d50ac31.tar.gz yosys-7b01ba384f1374d6a6fb3d40d7dc5fd03d50ac31.tar.bz2 yosys-7b01ba384f1374d6a6fb3d40d7dc5fd03d50ac31.zip | |
Improved make rules for profiling and debugging
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions