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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-18 11:56:16 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-18 11:56:16 +0200 |
| commit | 5998c101a46c5121db0fa73b3af1f180a73d7fd5 (patch) | |
| tree | 8cfba156ab62fd7e61b1945cb1b6c6a983bcb0f0 /backends/verilog | |
| parent | 9bc703b9648c041f79f5a3460f93dfc6154a669b (diff) | |
| download | yosys-5998c101a46c5121db0fa73b3af1f180a73d7fd5.tar.gz yosys-5998c101a46c5121db0fa73b3af1f180a73d7fd5.tar.bz2 yosys-5998c101a46c5121db0fa73b3af1f180a73d7fd5.zip | |
Added $sr, $dffsr and $dlatch cell types
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 29 |
1 files changed, 1 insertions, 28 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 5b7b601dd..e0794ad6c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -573,34 +573,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$sr") - { - RTLIL::SigSpec sig_set, sig_reset; - - std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections["\\Q"], reg_name); - - if (!out_is_reg_wire) - fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); - - fprintf(f, "%s" "always @*\n", indent.c_str()); - - fprintf(f, "%s" " %s <= (%s | ", indent.c_str(), reg_name.c_str(), reg_name.c_str()); - dump_cell_expr_port(f, cell, "S", false); - fprintf(f, ") & ~"); - dump_cell_expr_port(f, cell, "R", false); - fprintf(f, ";\n"); - - if (!out_is_reg_wire) { - fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Q"]); - fprintf(f, " = %s;\n", reg_name.c_str()); - } - - return true; - } - - // FIXME: $memrd, $memwr, $mem, $fsm + // FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm return false; } |