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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 12:33:56 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 12:33:56 +0200 |
| commit | 53655d173b2928328061c8440cc993508e951e1f (patch) | |
| tree | 87c12bdeb1a7cde96569efd1da18bee909b2f115 /backends/verilog | |
| parent | ffbb4e992e5312d8feafcc1c6c850ea06c3e09b2 (diff) | |
| download | yosys-53655d173b2928328061c8440cc993508e951e1f.tar.gz yosys-53655d173b2928328061c8440cc993508e951e1f.tar.bz2 yosys-53655d173b2928328061c8440cc993508e951e1f.zip | |
Added $global_clock verilog syntax support for creating $ff cells
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions