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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:58:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:58:59 -0700 |
| commit | 4cfef7897f4bac285853bf0f08ae366523ae76b4 (patch) | |
| tree | 238a71ec6696966652211fb79bd52c3c8c97eee7 /backends/verilog | |
| parent | 4486a98fd5928a4e3cdf9cd27c27b7dd821513bb (diff) | |
| parent | eaf3c247729365cec776e147f380ce59f7dccd4d (diff) | |
| download | yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.tar.gz yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.tar.bz2 yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.zip | |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 855409d0b..9967482d6 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -187,6 +187,10 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o { if (width < 0) width = data.bits.size() - offset; + if (width == 0) { + f << "\"\""; + return; + } if (nostr) goto dump_hex; if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) { @@ -340,6 +344,10 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) { + if (GetSize(sig) == 0) { + f << "\"\""; + return; + } if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk()); } else { |