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author | Henner Zeller <h.zeller@acm.org> | 2018-07-20 23:41:18 -0700 |
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committer | Henner Zeller <h.zeller@acm.org> | 2018-07-20 23:51:06 -0700 |
commit | 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc (patch) | |
tree | 39d2caa1122c32a56231ecd99fe3364721b53c3c /backends/verilog | |
parent | 323f6f6f6006eadcaec180f2cc1556f1f3303be3 (diff) | |
download | yosys-3aa4484a3cd9a2e82fddd499cde575eaf8c565cc.tar.gz yosys-3aa4484a3cd9a2e82fddd499cde575eaf8c565cc.tar.bz2 yosys-3aa4484a3cd9a2e82fddd499cde575eaf8c565cc.zip |
Consistent use of 'override' for virtual methods in derived classes.
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
Diffstat (limited to 'backends/verilog')
-rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b50dc12af..44e4e5f97 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1482,7 +1482,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) struct VerilogBackend : public Backend { VerilogBackend() : Backend("verilog", "write design to Verilog file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1550,7 +1550,7 @@ struct VerilogBackend : public Backend { log("this command is called on a design with RTLIL processes.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing Verilog backend.\n"); |