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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 14:48:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 14:48:58 -0700 |
| commit | 32561332b21b7b072fa6619f0bbb29a69cb30f33 (patch) | |
| tree | fd36bc3cc157d6bbef5d299835ac4e28d16ecd3c /backends/verilog | |
| parent | bf92218e0f3b18675b07971effab0992ad43553b (diff) | |
| download | yosys-32561332b21b7b072fa6619f0bbb29a69cb30f33.tar.gz yosys-32561332b21b7b072fa6619f0bbb29a69cb30f33.tar.bz2 yosys-32561332b21b7b072fa6619f0bbb29a69cb30f33.zip | |
Update doc for synth_xilinx
Diffstat (limited to 'backends/verilog')
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