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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-17 12:12:04 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-17 12:12:04 +0200 |
| commit | 1b00861d0a3bba0b609eecde504d8a4f2f9d973d (patch) | |
| tree | 0b533780cef7653d9d934be7008af6107e9453fb /backends/verilog | |
| parent | 274c51487937e3ca37c3520e98e996cb5918e982 (diff) | |
| download | yosys-1b00861d0a3bba0b609eecde504d8a4f2f9d973d.tar.gz yosys-1b00861d0a3bba0b609eecde504d8a4f2f9d973d.tar.bz2 yosys-1b00861d0a3bba0b609eecde504d8a4f2f9d973d.zip | |
Improved opt_reduce handling of mem wr_en mux bits
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions