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| author | Jannis Harder <me@jix.one> | 2023-02-13 14:00:38 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-02-13 14:00:38 +0100 |
| commit | 160eeab2bbf6274e0a667fdc334ddcf70c81bfb0 (patch) | |
| tree | 82f988af149ef0db950010f9ea10b50fb6d1bb76 /backends/verilog | |
| parent | 6d021f04d4363c971d3a4d40948f89a4699f45f3 (diff) | |
| download | yosys-160eeab2bbf6274e0a667fdc334ddcf70c81bfb0.tar.gz yosys-160eeab2bbf6274e0a667fdc334ddcf70c81bfb0.tar.bz2 yosys-160eeab2bbf6274e0a667fdc334ddcf70c81bfb0.zip | |
verilog_backend: Do not run bwmuxmap even if in expr mode
While bwmuxmap generates equivalent logic, it doesn't propagate x bits
in the same way, which can be relevant when writing verilog.
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 0a9c0590e..3da168960 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2329,7 +2329,6 @@ struct VerilogBackend : public Backend { if (!noexpr) { Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); - Pass::call(design, "bwmuxmap"); } Pass::call(design, "clean_zerowidth"); log_pop(); |