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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 09:55:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 09:55:14 -0700 |
| commit | 0c3ed73dade2488d0add1a3e6e82b148171f2d66 (patch) | |
| tree | db7e62f33b494a0fb67207dab69ee3c80d3d9242 /backends/verilog | |
| parent | 33862d04451ba58ce2b51c1e11abf86b65c3f018 (diff) | |
| download | yosys-0c3ed73dade2488d0add1a3e6e82b148171f2d66.tar.gz yosys-0c3ed73dade2488d0add1a3e6e82b148171f2d66.tar.bz2 yosys-0c3ed73dade2488d0add1a3e6e82b148171f2d66.zip | |
Count $_NOT_ cells turned into $luts
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions