Add clean_zerowidth pass, use it for Verilog output.

This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.

1 files changed, 2 insertions, 0 deletions

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 13c78c526..e4781ef3e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2300,6 +2300,8 @@ struct VerilogBackend : public Backend {
 			extmem_prefix = filename.substr(0, filename.rfind('.'));
 		}
 
+		Pass::call(design, "clean_zerowidth");
+
 		design->sort();
 
 		*f << stringf("/* Generated by %s */\n", yosys_version_str);