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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 22:33:35 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 22:33:35 -0700 |
| commit | f984e0cb345c7cec85eb9b90a13faacffa2e3fa2 (patch) | |
| tree | 461629a0ef6922aeec6dcf377e158e0d28086cae /backends/verilog/verilog_backend.cc | |
| parent | 375fcbe5113db80a92b950e5aca7df17add67acf (diff) | |
| download | yosys-f984e0cb345c7cec85eb9b90a13faacffa2e3fa2.tar.gz yosys-f984e0cb345c7cec85eb9b90a13faacffa2e3fa2.tar.bz2 yosys-f984e0cb345c7cec85eb9b90a13faacffa2e3fa2.zip | |
Another typo
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
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