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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
| commit | 8fe0a961b306ef0c9c5de912833c6d92aed5f363 (patch) | |
| tree | 10325fb4b9a5d9a481177f0360fdbb8026e66367 /backends/verilog/verilog_backend.cc | |
| parent | a20ed260e1b12da64bc4b40682c53145f6ffe827 (diff) | |
| parent | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (diff) | |
| download | yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.gz yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.bz2 yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.zip | |
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 83d83f488..855409d0b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1770,7 +1770,7 @@ struct VerilogBackend : public Backend { *f << stringf("/* Generated by %s */\n", yosys_version_str); for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { - if (it->second->get_bool_attribute("\\blackbox") != blackboxes) + if (it->second->get_blackbox_attribute() != blackboxes) continue; if (selected && !design->selected_whole_module(it->first)) { if (design->selected_module(it->first)) |