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| author | whitequark <whitequark@whitequark.org> | 2020-04-14 13:53:52 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-14 13:53:52 +0000 |
| commit | 7025881a5e8c4feb077d296f996683094e2a313a (patch) | |
| tree | 5f27feddbffbac9922dad821b8576d72fbdd9329 /backends/verilog/verilog_backend.cc | |
| parent | 759283fa65b1195ebe3a5bc6890ec622febca0eb (diff) | |
| parent | 9c64d37a4c3279ca037d4eae79f6ea60ca582457 (diff) | |
| download | yosys-7025881a5e8c4feb077d296f996683094e2a313a.tar.gz yosys-7025881a5e8c4feb077d296f996683094e2a313a.tar.bz2 yosys-7025881a5e8c4feb077d296f996683094e2a313a.zip | |
Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilation
write_cxxrtl: enable separate compilation
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 5467e250b..11b2ae10f 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1984,7 +1984,7 @@ struct VerilogBackend : public Backend { extra_args(f, filename, args, argidx); if (extmem) { - if (filename.empty()) + if (filename == "<stdout>") log_cmd_error("Option -extmem must be used with a filename.\n"); extmem_prefix = filename.substr(0, filename.rfind('.')); } |