Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig

1 files changed, 18 insertions, 4 deletions

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a7f329ef8..66a9e70d3 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 	}
 }
 
-void dump_reg_init(std::ostream &f, SigSpec sig)
+void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
 {
 	Const initval;
 	bool gotinit = false;
@@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig)
 	}
 
 	if (gotinit) {
-		f << " = ";
+		if (write_equals) f << " = ";
 		dump_const(f, initval);
 	}
 }
@@ -1247,7 +1247,14 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	dump_attributes(f, indent, cell->attributes);
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
-	if (!defparam && cell->parameters.size() > 0) {
+	std::string init;
+	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+		std::stringstream ss;
+		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
+		init = ss.str();
+	}
+
+	if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {
 		f << stringf(" #(");
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			if (it != cell->parameters.begin())
@@ -1257,6 +1264,11 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(")");
 		}
+		if (!init.empty()) {
+			if (!cell->parameters.empty())
+				f << stringf(",");
+			f << stringf("\n%s  .INIT(%s)", indent.c_str(), init.c_str());
+		}
 		f << stringf("\n%s" ")", indent.c_str());
 	}
 
@@ -1298,13 +1310,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 	f << stringf("\n%s" ");\n", indent.c_str());
 
-	if (defparam && cell->parameters.size() > 0) {
+	if (defparam && (cell->parameters.size() > 0 || !init.empty())) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
 			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(";\n");
 		}
+		if (!init.empty())
+			f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str());
 	}
 
 }