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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-12 09:46:15 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-12 09:46:15 +0200 |
| commit | e92998a79cec635270a350117eddb52c6232f388 (patch) | |
| tree | 2da5aa030336680bfa79b14e35f069123c0ba09e /backends/verilog/Makefile.inc | |
| parent | c71785d65e9775093b24ce684ed4fbe93bedb04d (diff) | |
| download | yosys-e92998a79cec635270a350117eddb52c6232f388.tar.gz yosys-e92998a79cec635270a350117eddb52c6232f388.tar.bz2 yosys-e92998a79cec635270a350117eddb52c6232f388.zip | |
Minor bugfix in FSM reset state detection
Diffstat (limited to 'backends/verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions