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| author | David Shah <dave@ds0.me> | 2019-11-21 20:27:19 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-11-21 20:27:19 +0000 |
| commit | 9e4801cca7bf346ac4d2ca0feaacda1e4bb27ac2 (patch) | |
| tree | 9310f511fb6aa2fc61d3660d7271f8cc61f19361 /backends/verilog/Makefile.inc | |
| parent | 0ac330bb81946081a3ab9ae45ef5aa7122dcb786 (diff) | |
| download | yosys-9e4801cca7bf346ac4d2ca0feaacda1e4bb27ac2.tar.gz yosys-9e4801cca7bf346ac4d2ca0feaacda1e4bb27ac2.tar.bz2 yosys-9e4801cca7bf346ac4d2ca0feaacda1e4bb27ac2.zip | |
sv: Correct parsing of always_comb, always_ff and always_latch
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'backends/verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions