diff options
| author | Xiretza <xiretza@xiretza.xyz> | 2020-04-08 19:30:47 +0200 |
|---|---|---|
| committer | Xiretza <xiretza@xiretza.xyz> | 2020-05-28 22:59:03 +0200 |
| commit | 17163cf43a6b6eec9aac44f6a4463dda54b8ed68 (patch) | |
| tree | 02dd1e144c36eb40565cbb792726c7d8d4573eb4 /backends/verilog/Makefile.inc | |
| parent | 0d99522b3c2ca2502129110e09f9988874e37abc (diff) | |
| download | yosys-17163cf43a6b6eec9aac44f6a4463dda54b8ed68.tar.gz yosys-17163cf43a6b6eec9aac44f6a4463dda54b8ed68.tar.bz2 yosys-17163cf43a6b6eec9aac44f6a4463dda54b8ed68.zip | |
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
Diffstat (limited to 'backends/verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions