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authorClifford Wolf <clifford@clifford.at>2019-04-20 20:51:54 +0200
committerGitHub <noreply@github.com>2019-04-20 20:51:54 +0200
commitf84a84e3f1a27b361c21fcd30fcf50c1a6586629 (patch)
tree2d6b8acf72eead2e314295326d567e17e0c66871 /backends/table/table.cc
parente3687f6f4e10789223213949b8490bd83ec285f2 (diff)
parentf3ad8d680a3195ab9525b0a8b3f8dbff9d5e6e24 (diff)
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Merge pull request #943 from YosysHQ/clifford/whitebox
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
Diffstat (limited to 'backends/table/table.cc')
-rw-r--r--backends/table/table.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/table/table.cc b/backends/table/table.cc
index b75169ea4..796f18059 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -67,7 +67,7 @@ struct TableBackend : public Backend {
for (auto module : design->modules())
{
- if (module->get_bool_attribute("\\blackbox"))
+ if (module->get_blackbox_attribute())
continue;
SigMap sigmap(module);