diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
| commit | f9946232adf887e5aa4a48c64f88eaa17e424009 (patch) | |
| tree | 39594b3287c3369752668456c4a6b1735fb66e77 /backends/spice | |
| parent | d7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff) | |
| download | yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.gz yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.bz2 yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.zip | |
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'backends/spice')
| -rw-r--r-- | backends/spice/spice.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 077368771..ef31e06a9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -68,7 +68,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de RTLIL::Module *mod = design->modules.at(cell->type); std::vector<RTLIL::Wire*> ports; - for (auto wire_it : mod->wires) { + for (auto wire_it : mod->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; @@ -195,7 +195,7 @@ struct SpiceBackend : public Backend { } std::vector<RTLIL::Wire*> ports; - for (auto wire_it : module->wires) { + for (auto wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; |