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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-22 20:12:18 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-22 20:12:18 +0100 |
| commit | e5eb3d2c8ace00aeedec410d17a4972a76782089 (patch) | |
| tree | 0c9b4c652028fd41df3e5d2cc1399007083f1c45 /backends/simplec | |
| parent | ee8a7589e09efeb38cbc5ee6fd241758d6637fe2 (diff) | |
| parent | 182d84ad54cff315e7afb07f5353a477e4c410f4 (diff) | |
| download | yosys-e5eb3d2c8ace00aeedec410d17a4972a76782089.tar.gz yosys-e5eb3d2c8ace00aeedec410d17a4972a76782089.tar.bz2 yosys-e5eb3d2c8ace00aeedec410d17a4972a76782089.zip | |
Merge pull request #757 from whitequark/manual_mem
manual: document $meminit cell and memory_* passes
Diffstat (limited to 'backends/simplec')
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