Merge remote-tracking branch 'origin/master' into feature/python_bindings

2 files changed, 6 insertions, 6 deletions

diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc
index c9656caff..6f2ccbe20 100644
--- a/backends/simplec/simplec.cc
+++ b/backends/simplec/simplec.cc
@@ -742,13 +742,13 @@ struct SimplecWorker
 
 struct SimplecBackend : public Backend {
 	SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    write_simplec [options] [filename]\n");
 		log("\n");
-		log("Write simple C code for simulating the design. The C code writen can be used to\n");
+		log("Write simple C code for simulating the design. The C code written can be used to\n");
 		log("simulate the design in a C environment, but the purpose of this command is to\n");
 		log("generate code that works well with C-based formal verification.\n");
 		log("\n");
@@ -761,7 +761,7 @@ struct SimplecBackend : public Backend {
 		log("THIS COMMAND IS UNDER CONSTRUCTION\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		reserved_cids.clear();
 		id2cid.clear();
diff --git a/backends/simplec/test00_uut.v b/backends/simplec/test00_uut.v
index 744dbe9e3..92329a6f9 100644
--- a/backends/simplec/test00_uut.v
+++ b/backends/simplec/test00_uut.v
@@ -3,12 +3,12 @@ module test(input [31:0] a, b, c, output [31:0] x, y, z, w);
   unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
   assign z = a ^ b ^ c, w = z;
 endmodule
-  
+
 module unit_x(input [31:0] a, b, c, output [31:0] x);
   assign x = (a & b) | c;
 endmodule
-  
+
 module unit_y(input [31:0] a, b, c, output [31:0] y);
   assign y = a & (b | c);
 endmodule
-  
+