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author	Yosys Bot <yosys-bot@symbioticeda.com>	2020-10-22 00:10:06 +0000
committer	Yosys Bot <yosys-bot@symbioticeda.com>	2020-10-22 00:10:06 +0000
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# nextpnr Generic Architecture Instead of implementing the [C++ API](archapi.md), you can programmatically build up a description of an FPGA using the generic architecture and the Python API. A basic packer is provided that supports LUTs, flipflops and IO buffer insertion. Packing could also be implemented using the Python API. At present there is no support for cell timing in the generic architecture. This will be worked on in the future. ## Python API All identifiers (`IdString`) are automatically converted to and from a Python string, so no manual conversion is required. Argument names are included in the Python bindings, so named arguments may be used. ### void addWire(IdString name, IdString type, int x, int y); Adds a wire with a name, type (for user purposes only, ignored by all nextpnr code other than the UI) to the FPGA description. x and y give a nominal location of the wire for delay estimation purposes. Delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is not of importance. ### addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc); Adds a pip (programmable connection between two named wires). Pip delays that correspond to delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is otherwise not of importance. Loc is constructed using `Loc(x, y, z)`. 'z' for pips is only important if region constraints (e.g. for partial reconfiguration regions) are used. ### void addBel(IdString name, IdString type, Loc loc, bool gb); Adds a bel to the FPGA description. Bel type should match the type of cells in the netlist that are placed at this bel (see below for information on special bel types supported by the packer). Loc is constructed using `Loc(x, y, z)` and must be unique. ### void addBelInput(IdString bel, IdString name, IdString wire); ### void addBelOutput(IdString bel, IdString name, IdString wire); ### void addBelInout(IdString bel, IdString name, IdString wire); Adds an input, output or inout pin to a bel, with an associated wire. Note that both `bel` and `wire` must have been created before calling this function. ### void addGroupBel(IdString group, IdString bel); ### void addGroupWire(IdString group, IdString wire); ### void addGroupPip(IdString group, IdString pip); ### void addGroupGroup(IdString group, IdString grp); Add a bel, wire, pip or subgroup to a group, which will be created if it doesn't already exist. Groups are purely for visual presentation purposes in the user interface and are not used by any place-and-route algorithms.


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