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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
| commit | c094c53de83707a5bf1b268640283f1dde235873 (patch) | |
| tree | 27e480f63e0d34d8cbfcf8fcf29472c198381296 /backends/intersynth | |
| parent | 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff) | |
| download | yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.gz yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.bz2 yosys-c094c53de83707a5bf1b268640283f1dde235873.zip | |
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'backends/intersynth')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 832922def..a4cad5add 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -28,8 +28,6 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig) { - sig.optimize(); - if (sig.chunks().size() != 1) error: log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig)); |