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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-12 17:42:57 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-12 17:42:57 +0100 |
| commit | 76c4ee096bba99f787dd042bd9a6e988cf72f2dc (patch) | |
| tree | 2a50ba861a2c273bfd01a160758a53f079c38ac1 /backends/intersynth | |
| parent | 828303791b5f4a50a52d4749be42caac9819bf2a (diff) | |
| download | yosys-76c4ee096bba99f787dd042bd9a6e988cf72f2dc.tar.gz yosys-76c4ee096bba99f787dd042bd9a6e988cf72f2dc.tar.bz2 yosys-76c4ee096bba99f787dd042bd9a6e988cf72f2dc.zip | |
Do not eagerly fix port widths on parameterized cells
Diffstat (limited to 'backends/intersynth')
0 files changed, 0 insertions, 0 deletions