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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
| commit | 295e352ba6aa1bd71431abc21a8f93735968cae6 (patch) | |
| tree | 2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /backends/intersynth | |
| parent | c854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff) | |
| download | yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.tar.gz yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.tar.bz2 yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.zip | |
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'backends/intersynth')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index a3f61eeb5..402c3e7c4 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend { RTLIL::Module *module = module_it.second; SigMap sigmap(module); - if (module->get_bool_attribute("\\placeholder")) + if (module->get_bool_attribute("\\blackbox")) continue; if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0) continue; |