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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
| commit | 88d5185596a0cc8319658463a31b20644d90dd6b (patch) | |
| tree | 106f178d42a54403218f93cae2807d6e67981599 /backends/intersynth/intersynth.cc | |
| parent | 282cc77604a9a855c303869321d4179790b0b64b (diff) | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| download | yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.gz yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.bz2 yosys-88d5185596a0cc8319658463a31b20644d90dd6b.zip | |
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
Diffstat (limited to 'backends/intersynth/intersynth.cc')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index b0e3cd252..809a0fa09 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -108,7 +108,7 @@ struct IntersynthBackend : public Backend { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); libs.push_back(lib); } @@ -183,7 +183,7 @@ struct IntersynthBackend : public Backend { if (param.second.bits.size() != 32) { node_code += stringf(" %s '", RTLIL::id2cstr(param.first)); for (int i = param.second.bits.size()-1; i >= 0; i--) - node_code += param.second.bits[i] == RTLIL::S1 ? "1" : "0"; + node_code += param.second.bits[i] == State::S1 ? "1" : "0"; } else node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int()); } |