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| author | whitequark <whitequark@whitequark.org> | 2020-08-27 11:24:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-27 11:24:06 +0000 |
| commit | 702f7c0253dcf9410050586a5e56da044e3277a3 (patch) | |
| tree | ab94c9121ceb78152a538843e82f69228e938dde /backends/intersynth/intersynth.cc | |
| parent | 880df4c89763464b471b1e2044f3f296bb3332b4 (diff) | |
| parent | 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e (diff) | |
| download | yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.gz yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.bz2 yosys-702f7c0253dcf9410050586a5e56da044e3277a3.zip | |
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
Replace "ILANG" with "RTLIL" everywhere
Diffstat (limited to 'backends/intersynth/intersynth.cc')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 98a14173b..a6b36de6c 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -59,7 +59,7 @@ struct IntersynthBackend : public Backend { log(" do not generate celltypes and conntypes commands. i.e. just output\n"); log(" the netlists. this is used for postsilicon synthesis.\n"); log("\n"); - log(" -lib <verilog_or_ilang_file>\n"); + log(" -lib <verilog_or_rtlil_file>\n"); log(" Use the specified library file for determining whether cell ports are\n"); log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); @@ -108,7 +108,7 @@ struct IntersynthBackend : public Backend { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); } |