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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:06:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:06:57 -0700 |
| commit | abc40924ed5dc4aba91c7f1e83ca90f54e9eb455 (patch) | |
| tree | 937476067fef6b0931a63a83ef73c0add3eb0d47 /backends/ilang | |
| parent | ebe29b66593414d0317879359d1f1d1f61a9ecc4 (diff) | |
| download | yosys-abc40924ed5dc4aba91c7f1e83ca90f54e9eb455.tar.gz yosys-abc40924ed5dc4aba91c7f1e83ca90f54e9eb455.tar.bz2 yosys-abc40924ed5dc4aba91c7f1e83ca90f54e9eb455.zip | |
Use ABC to convert from AIGER to Verilog
Diffstat (limited to 'backends/ilang')
0 files changed, 0 insertions, 0 deletions