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| author | whitequark <whitequark@whitequark.org> | 2019-12-10 20:09:24 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-09 04:08:36 +0000 |
| commit | 5157691f0eca5c5312524483491309a7e07d9710 (patch) | |
| tree | c34bcf4b3da5423ac91ea318d4817c70aa8670c9 /backends/edif | |
| parent | d6d727342112eb89451407bd1d9954b8279bd015 (diff) | |
| download | yosys-5157691f0eca5c5312524483491309a7e07d9710.tar.gz yosys-5157691f0eca5c5312524483491309a7e07d9710.tar.bz2 yosys-5157691f0eca5c5312524483491309a7e07d9710.zip | |
write_cxxrtl: statically schedule comb logic and localize wires.
This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
Diffstat (limited to 'backends/edif')
0 files changed, 0 insertions, 0 deletions