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authorClifford Wolf <clifford@clifford.at>2019-04-20 20:51:54 +0200
committerGitHub <noreply@github.com>2019-04-20 20:51:54 +0200
commitf84a84e3f1a27b361c21fcd30fcf50c1a6586629 (patch)
tree2d6b8acf72eead2e314295326d567e17e0c66871 /backends/edif/edif.cc
parente3687f6f4e10789223213949b8490bd83ec285f2 (diff)
parentf3ad8d680a3195ab9525b0a8b3f8dbff9d5e6e24 (diff)
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Merge pull request #943 from YosysHQ/clifford/whitebox
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
Diffstat (limited to 'backends/edif/edif.cc')
-rw-r--r--backends/edif/edif.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 7e30b67af..6d9469538 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -178,7 +178,7 @@ struct EdifBackend : public Backend {
for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
- if (module->get_bool_attribute("\\blackbox"))
+ if (module->get_blackbox_attribute())
continue;
if (top_module_name.empty())
@@ -192,7 +192,7 @@ struct EdifBackend : public Backend {
for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
- if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
+ if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_blackbox_attribute()) {
lib_cell_ports[cell->type];
for (auto p : cell->connections())
lib_cell_ports[cell->type][p.first] = GetSize(p.second);
@@ -302,7 +302,7 @@ struct EdifBackend : public Backend {
*f << stringf(" (technology (numberDefinition))\n");
for (auto module : sorted_modules)
{
- if (module->get_bool_attribute("\\blackbox"))
+ if (module->get_blackbox_attribute())
continue;
SigMap sigmap(module);