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| author | whitequark <whitequark@whitequark.org> | 2020-04-17 21:36:59 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-17 21:36:59 +0000 |
| commit | d42530b7bba58d2f4c0b435b7c2d6ece5941e0e3 (patch) | |
| tree | f7caafcfa65ac31863def384bd6c804a8c846382 /backends/cxxrtl/cxxrtl.cc | |
| parent | 67fbc00a1824aafb2af2e7c4b7a9590c7bc718fa (diff) | |
| parent | e7ad209b15490c512049310643fdf137a4be1687 (diff) | |
| download | yosys-d42530b7bba58d2f4c0b435b7c2d6ece5941e0e3.tar.gz yosys-d42530b7bba58d2f4c0b435b7c2d6ece5941e0e3.tar.bz2 yosys-d42530b7bba58d2f4c0b435b7c2d6ece5941e0e3.zip | |
Merge pull request #1955 from whitequark/cxxrtl-sync_always
cxxrtl: correctly handle `sync always` rules
Diffstat (limited to 'backends/cxxrtl/cxxrtl.cc')
| -rw-r--r-- | backends/cxxrtl/cxxrtl.cc | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc index e4fa430f3..b210b9e7f 100644 --- a/backends/cxxrtl/cxxrtl.cc +++ b/backends/cxxrtl/cxxrtl.cc @@ -1076,24 +1076,34 @@ struct CxxrtlWorker { log_assert(proc->root_case.attributes.empty()); dump_case_rule(&proc->root_case); for (auto sync : proc->syncs) { - RTLIL::SigBit sync_bit = sync->signal[0]; - sync_bit = sigmaps[sync_bit.wire->module](sync_bit); + RTLIL::SigBit sync_bit; + if (!sync->signal.empty()) { + sync_bit = sync->signal[0]; + sync_bit = sigmaps[sync_bit.wire->module](sync_bit); + } pool<std::string> events; switch (sync->type) { case RTLIL::STp: + log_assert(sync_bit.wire != nullptr); events.insert("posedge_" + mangle(sync_bit)); break; case RTLIL::STn: + log_assert(sync_bit.wire != nullptr); events.insert("negedge_" + mangle(sync_bit)); + break; case RTLIL::STe: + log_assert(sync_bit.wire != nullptr); events.insert("posedge_" + mangle(sync_bit)); events.insert("negedge_" + mangle(sync_bit)); break; + case RTLIL::STa: + events.insert("true"); + break; + case RTLIL::ST0: case RTLIL::ST1: - case RTLIL::STa: case RTLIL::STg: case RTLIL::STi: log_assert(false); |